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HD74HC173
4-bit D-type Register (with 3-state outputs)
REJ03D0583-0300 Rev.3.00 Jan 31, 2006
Description
The four D type Flip-Flops operate synchronously from a common clock. The 3-state outputs allow the device to be used in bus organized systems. The outputs are placed in the 3-stage mode when either of the output disable pins are in the logic high level. The input disable allows the flip-flops to remain in their present states without having to disrupt the clock. If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs, forcing the flip-flops to remain in the same state. Clearing is enabled by taking the clear input to a logic high level. The data outputs change state on the positive going edge of the clock.
Features
* * * * * * High Speed Operation: tpd (Clock to Q) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 A max Low Quiescent Supply Current: ICC (static) = 4 A max (Ta = 25C) Ordering Information
Part Name HD74HC173P HD74HC173FPEL HD74HC173RPEL Package Type DILP-16 pin SOP-16 pin (JEITA) SOP-16 pin (JEDEC) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) PRSP0016DG-A (FP-16DNV) Package Abbreviation P FP RP -- EL (2,000 pcs/reel) EL (2,500 pcs/reel) Taping Abbreviation (Quantity)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs Data Enable Clear H L L L L L Clock X L G1 X X H X L L G2 X X X H L L Data D X X X X L H Output Q L Q0 Q0 Q0 L H
Note: When either M or N (or both) is (are) high the output is disabled to the high-impedance state; however sequential operation of the flip-flops is not affected. QAo to QHo = Outputs remain unchanged. QAn to QGn = Data shifted from the previous stage on a positive edge at the clock input. H: High level L: Low level X: Irrelevant
Rev.3.00, Jan 31, 2006 page 1 of 7
HD74HC173
Pin Arrangement
Output Control
M1 N2 1Q 3 2Q 4 Output Control Clear 1Q 2Q 3Q 4Q 1D 2D 3D 4D
16 VCC 15 Clear 14 1D 13 2D 12 3D 11 4D 10 G2 9 G1 Data Enable Input Data Input
Output
3Q 5 4Q 6 Clock 7 GND 8
CK Data Enable
(Top view)
Logic Diagram
VCC 1Q
1D
D C C
Q R Q
2D
D C C
Q R Q
VCC 2Q
3D
D C C
Q R Q
VCC 3Q
4D G1 G2 Clock Clear Control M Control N
D C C
Q R Q
VCC 4Q
Rev.3.00, Jan 31, 2006 page 2 of 7
HD74HC173
Absolute Maximum Ratings
Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC Vin, Vout IIK, IOK IO ICC or IGND PT Tstg Ratings -0.5 to 7.0 -0.5 to VCC +0.5 20 35 75 500 -65 to +150 Unit V V mA mA mA mW C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time*1 Note: Symbol VCC VIN, VOUT Ta tr, tf Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500 0 to 400 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Unit V V C ns Conditions
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
Electrical Characteristics
Item Input voltage Symbol VCC (V) VIH 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 6.0 Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- -- Ta = 25C Typ Max -- -- -- -- -- -- 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.5 0.1 4.0 Ta = -40 to+85C Unit Min Max 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 5.0 1.0 40 V Test Conditions
VIL
V
Output voltage
VOH
V
Vin = VIH or VIL IOH = -20 A
VOL
V
Vin = VIH or VIL
IOH = -6 mA IOH = -7.8 mA IOL = 20 A
IOL = 6 mA IOL = 7.8 mA A Vin = VIH or VIL, Vout = VCC or GND A Vin = VCC or GND A Vin = VCC or GND, Iout = 0 A
Off-state output current Input current Quiescent supply current
IOZ Iin ICC
Rev.3.00, Jan 31, 2006 page 3 of 7
HD74HC173
Switching Characteristics
(CL = 50 pF, Input tr = tf = 6 ns)
Item Maximum clock frequency Propagation delay time Symbol VCC (V) fmax 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- Ta = 25C Ta = -40 to +85C Unit Min Typ Max Min Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100 20 17 90 18 15 5 5 5 80 16 14 -- -- -- -- -- -- -- -- 14 -- -- 14 -- -- 12 -- -- 12 -- -- 4 - -- 0 -- -- -2 -- -- 4 -- -- 4 -- 5 5 27 32 175 35 30 150 30 26 150 30 26 150 30 26 -- -- -- -- -- -- -- -- -- -- -- -- 60 12 10 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 125 25 21 115 23 20 5 5 5 100 20 17 -- -- -- -- 4 21 25 220 44 37 190 38 33 190 38 33 190 38 33 -- -- -- -- -- -- -- -- -- -- -- -- 75 15 13 10 MHz Test Conditions
tPLH, tPHL
ns
Clock to Q
tPHL
ns
Clear to Q
Enable time
tZH, tZL
ns
Disable time
tHZ, tLZ
ns
Setup time
tsu
ns
Removal time
trem
ns
Hold time
th
ns
Pulse width
tw
ns
Output rise/fall time Input capacitance
tTLH, tTHL
ns
Cin
pF
Test Circuit
Output 1K CL OPEN GND VCC TEST t PLH / t PHL t ZH/ t HZ t ZL / t LZ S2 OPEN GND VCC
S2
Note 1. CL includes probe and jig capacitance
Rev.3.00, Jan 31, 2006 page 4 of 7
HD74HC173
Waveforms
* Waveform - 1
tr
90%
tf VCC
50% 10%
Clear
50% 10%
tr
90% 90%
tW tf
0V tW (H) tW (L) VCC
50% 50% 50%
trem
Clock
10% 10%
0V tsu th
50%
tsu
th VCC
50%
90%
90% 10% 50% 10%
Data tf tPHL
90%
tr tPLH
90% 50% 10%
0V tPHL VOH
50%
Output QH tTHL
50% 10%
tTLH
VOL
Note 1. Input pulse : PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns
* Waveform - 2
90 % Output Control
tf
tr 90 % 50 % 10 % t LZ VCC 0V VOH
50 % 10 % t ZL
Waveform - A t ZH Waveform - B
50 % t HZ
10 %
VOL VOH VOL
50 %
90 %
Notes 1. Input pulse PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. Waveform - A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. waveform - B is for an output with internal conditions such that the output is high except when disabled by the output control.
Rev.3.00, Jan 31, 2006 page 5 of 7
HD74HC173
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
E
A1
A
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max
e D E
L
1
A A1
e
bp
e1
b c b c
p 3
e Z ( Ni/Pd/Au plating ) L
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c
0.00
0.10
0.20 2.20
0.34
0.40
0.46
0.15
1
0.20
0.25
A
c
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.3.00, Jan 31, 2006 page 6 of 7
HD74HC173
JEITA Package Code P-SOP16-3.95x9.9-1.27 RENESAS Code PRSP0016DG-A Previous Code FP-16DNV MASS[Typ.] 0.15g
*1
D 9
F
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
Index mark
*2
E
HE
c
Reference Symbol
Dimension in Millimeters Min Nom 9.90 3.95 Max 10.30
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c c
1
0.10
0.14
0.25 1.75
0.34
0.40
0.46
0.15
0.20
0.25
HE
0 5.80 6.10 1.27
8 6.20
A
A1
L y
e x y
0.25 0.15 0.635 0.40
1
Detail F
Z L L 0.60 1.08
1.27
Rev.3.00, Jan 31, 2006 page 7 of 7
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